Timex FDD 3Timex FDD 3 is a computer with Z80, 16kB/64kB RAM, 128 bytes of ROM (however the chip has 2kB), floppy disk controller, two RS232C channels and 6bit full-duplex cable to Timex Interface M-397. It need +5V/+12V power supply unit. Four 3" or 5.25" or 3.5" floppy drives can be connected to the flat cable or white slot - they also need separate power supply. Usually there are 3 modules in the same cases. One is power supply unit, second is Timex FDD 3, third is 3" floppy drive. The power supply unit provides +5V/+12V for both the Timex FDD 3 and floppy drive unit. The interface can be connected to Timex 2048, ZX Spectrum 48kB. The Timex Sinclair 2068 needs Twister Board, ZX Spectrum 128K needs ROM upgrade in the interface. Timex Sinclair 2068 and Timex Computer 2068 may need also cartridge with ZX Spectrum compatibile ROM, unless the interface has Zebra ROM - in this case will work only with Timex 2068. The Timex FDD 3 has 16kB by factory and can be upgraded to 64kB RAM. (Or 4MB RAM, with YABUS.TF3.) The 16kB version can use only TOS A.2. With 64kB RAM, also TOS A.4, CP/M 2.2 and CPM22QED can be used. It could be hard to distinguish amount of memory from the picture. VersionsThe top board contains memory. There are at least two versions. First is smaller, contains eight 4116 and is connected with a wire tape. The second is a little bigger, contains two 4416 (or 4464) and is connected with many vertical wires. Upgrade to 64kB RAMThe two 4416 must be replaced with 4464. It could be hard to desolder them, as they are upside-down on the top board. Also another 74*157 like multiplexer must be added, but only one of four its gates is used. The A0 connected to pin 10 of the memory must be replaced with multiplexer output. As the inputs of the multiplexer should be connected A14 (A) and A0 (B). A15 can be connected to pin 3 of the ULA IHO35E, after cuting out ground from this pin. The selection line is on pin 1 of the 74LS157 on top board and also on pin 14 of the ULA. But this is not all. The PAL logic limits the memory access to first 16kB, because is conencted to 139 gate.
---_--- ---_---
(nc) ?1 20+ +5V /MREQ I1 16+ +5V
IRQ I2 19O /INT A15 I2 15I /IORQ
A5 I3 18O /FDC A14 I3 14I A6
/CX I4 17O RAM /SA O4 13I A7
/WR I5 16O /E0 - O5 12O /0X
/SA I6 15O /ROM - O6 11O /8X
A13 I7 14O /RS - O7 10O /4X
BOOT I8 13O /IN GND -8 9O /CX
/RD I9 12O /OUT -------
GND -10 11I /0X IC6 139
-------
IC9 PAL
A5,A6,A7,A13,A14,A15 - CPU adderess lines
/WR,/RD,/MREQ,/IORQ - CPU signal lines
IRQ - interrupt request from FDC
BOOT - latched bit 6 of #E0 port (enable ROM)
/SA - decoded memory of section A
/0X,/4X,/8X,/CX - decoded port lines
/FDC,/E0,/RS,/IN,/OUT - decoded port lines
/INT - interrupt output to CPU
/ROM - /CS signal for EPROM
RAM - /CS signal for memory ULA
The simplest solution is to cut the /SA signal between 139 and PAL and connect /MREQ there. This will enable the /ROM to be seen also in addresses #4000..#5FFF, #8000..#9FFF and #C000..#DFFF. This is not big problem, as the ROM is used only to read boot sector. The better solution, espcialy recomended for 128kB upgrade is to swap the signals: /MREQ on 139 with A13, A13 on PAL with /SA, /SA on PAL with /IORQ.This enables the ROM to be seen only in #0000..#1FFF. Upgrade to 128kB RAMThe simplest and cheapest upgrade from 16kB is to use 128kB SRAM chip. You don't have to add extra multiplexer. Just solder the SRAM chip under the EPROM socket and remove top board. Pins 18, 20, 21 and 24 of the EPROM socket must be cuted, as other signals go to SRAM in these places. Other EPROM socket pins can be soldered directly to SRAM (GND, D0..D7, A0..A10). Of course only half of the chip (64kB) is used in the standard way. When having 128kB it would be a shame to waste 64kB. For the bankswitching, the unused bits of #2F or #E0 ports can be used. The simplest bankswitching can use one extra bit as the last SRAM address line. But problem appears - when 64kB are switched at a time, how to write something into the other 64kB? Well, in the EPROM could be written a short code that takes byte(s) from the current bank, writes to the other and goes back to piervousely used one. The more complex soulution would require a multiplexer, that depending on address would provide current address lines (not switchable area) or bits stored in a latch (switchable area). The simplest of this would be a 74LS157 like with two bits of bank number. So, 32kB is fixed memory, while other 32kB can be switched. Well, the 74LS157 is already here and without DRAM on top board is useless. However, you would have to rewire it completely, as it is connected to A0..A3 and A7..A10. A solution compatibile to YABUS.TF3 would require a 74LS670 chip and some initialization code in ROM. Also, the half of IC6 (74LS139) would have to be used to distinguish between FDC port addresses (#C0..#C3) and memory switching addresses (#D0..#D3). Upgrade to 4MB RAMSee YABUS.TF3 link below. Pliki do pobrania
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