DivIDE : ZX Spectrum

DivIDE interface gives 8kB EEPROM, 32kB SRAM, hardware traps and IDE interface. There are firmwares (BIOSes) that reads FAT, simulates +D and D40/D80. They are exclusive and require separate harddisks, as each prefers own structures.

Memory map

• In normal mode, ROM0 and one of write-enabled RAM* is used. Traps are enabled.
• In MAPRAM mode (bit 6=1), ROM0 is replaced with RAM3, that gets write-protected (until CONMEM mode is selected). Traps are enabled. MAPRAM mode can be disabled only by power off. MAPRAM mode is used to test new ROM0 code.
• In CONMEM mode (bit 7=1), ROM0 is write-protected when jumper is closed, or write-enabled when open; one of write-enabled RAM* is used. Traps are disabled and the interface memory replaces ZXROM. CONMEM mode has highest priority and can be used to modify ROM0 or RAM3 for MAPRAM.

DiwIDE - an upgrade

DiwIDE has some upgrades to original project:

• Hardware traps are disabled when ROM0 of ZX Spectrum 128K is paged in. In original project the TR-DOS hardware traps were activated also in 128 BASIC. (This patch can make problem to run a snapshot with ROM0 selected. But such are quite rare as most of software use the ROM1 and ROM0 has different contents across ZX Spectrum 128K models. Also, the ROM0 can contain custom utility or operating system like NeOS.)
• More EEPROM. In present v212, a 32kB chip can be used (28C256) in place of 8kB (28C64); only PLCC, what is not compatibile to EEPROM like 29C010.
• More SRAM. In present v212, a 128kB or 512kB SRAM can be used, with battery backup.
• A possibility to page 16kB write-enabled RAM. This allows to run other operating systems like CP/M (only on ZX Spectrum 128K due to requiment for extra screen), ResiDOS, +3e. Also the exit traps (#1FF8..#1FFF) are disabled in this mode.

These all are options. With some small fixes on the board, the DiwIDE can be downgraded to full DivIDE compatibility.

Also, the design is corrected a bit:

• Added reset button.
• CompactFlash slot as an option to IDE 40pin slot.
• Internal ZX Spectrum bus - flat cable with through edge slot can be connected here or an upgrade board installed. For example: Kempston Joystick, AY-3-8910, Z80DMA, Real Time Clock, Plus D, Interface 1, Interface 2. As an option, memory access can be disabled in this slot, so there are no memory conflicts and firmware only uses I/O ports.
• Board enlarged for nice Z-19 case.
• PLCC socket for *ROM.
• ZX+3 jumper moved near edge slot.
• IDE slot is protected. The harddisk can damage itself when is powered from extral power suppy, while IDE cable on other side is grounded (in low impedance) by computer being off.

DiwIDE evalution board v212

This board was made to test possible ROM and RAM upgrade. The simplest solution was selected. It limits the ROM amount to 32kB, to provide compatibility to 8kB 28C64 in PLCC socket. Please do not consider this as final version.

#E3 port upgrade

There are four extra latches at #E3 (227) port. Bit 2 is extra address line for 128kB SRAM (the second is A13). Bits 3 and 4 are extra address lines for 32kB ROM. Bit 5, when set, forces the 16kB RAM mode - disables the ROM and write-protected RAM.

• RAM3H replaces ROM* in MAPRAM mode and is write protected then.
• The RAM*H is top 8kB of each RAM* 16kB RAM bank. The low part is not accessible in 8kB ROM + 8kB RAM mode.
• The ROM1, ROM2, ROM3 are present only for 32kB ROM.

• In MAPRAM mode, RAM3 and RAM7 are write-protected.
• In CONMEM mode, all RAM* are write-enabled and the selected one replaces ZXROM.

For 512kB SRAM version, also bits 3 and 4 are used as RAM address lines, so every of 4 ROM banks has own set of 8×8kB RAM banks. In 16kB RAM mode, there are 32 banks of 16kB.

Plans for next release - board v317+

Several pieces of v212 board were produced to evaluate possible solutions. Some are definiely better (like both IDE40 and CF slots in the same time), some are still analysed (like PLCC or DIL for ROM). Following things are considered:

• Replacing the ROM PLCC socket with DIL32. In DIL both 28C64 and 29F010 can be used, while their PLCC cases have different pinout.
• Allowing also 29*040 like EEPROMs (29C040 or cheaper 29F040).
• Removing the mixing of address and data lines from EPROM socket. Already done.
• Allowing the EEPROM to hold also the ZXROM contents (including two ZX128 ROM banks).
• Both CF and IDE40 support. CF at bottom of the board, IDE40 slot at top with pins cuted a bit. Done.
• Replacing the 74LS174 with 74LS175 will improve the 16kB RAM mode. Inverted bit 5 can disable TR-DOS traps, e.g. for CP/M. Otherwise OUT 32765,0 must be performed (ROM0 selected) or CONMEM mode forced.
• 512kB SRAM in SMD case mounted as default.
• MB-02 compatibility in matter of memory switching.

MB-02 memory compatibility

The 512kB RAM+512kB ROM is seen in two modes:

• in MB-02 mode: as 64 RAM/ROM pages of 16kB each,
• in DivIDE mode: as 16 blocks of 32kB RAM+8kB ROM.

There's an extra port at 23 address (compatibile to MB-02 memory mapper) that selects mode (bits 6 and 7), control write-protection (bit 5) and page/block (bits 4 to 0). Port 227 (#E3) is not touched in this solution.

Bit 7=0, bit 6=0 - select DivIDE mode, while bits 1..4 select the block (bits 0 and 4 are ignored). So 16 different firmware can be used, with DivIDE compatibility preserved (except ROM reprogramming, as 29F040 requires other procedure than 28C64). DivIDE traps are enabled and internal ZXROM of ZX Spectrum is used.

Bit 7=0, bit 6=1 - select RAM in MB-02 mode. Bits 0..4 selects the RAM page that replaces ZXROM. Bit 5 must be set to enable writing to the RAM. DivIDE traps are disabled.

Bit 7=1, bit 6=0 - select ROM in MB-02 mode. Bits 0..4 selects the ROM page that replaces ZXROM. Bit 5 must be set to enable writing to the 29F040 Flash EEPROM. (For correct writing set of proper commands must be send to it, according to 29F040 documentation.) DivIDE traps are disabled.

Bit 7=1, bit 6=1 - forces hard-reset. This can be used to unlock the 32765 (#7FFD) port of ZX128, that gets locked when bit 5 set while OUT, also to reset MAPRAM mode of DivIDE.

As the ROM in DivIDE mode is used last (top) 8kB of an odd ROM page (when seen in MB-02 mode).

The interface wakes up in DivIDE mode (like 0 written to 23 port).

Some of MB-02 software will work on this configuration. (But not all, as many require QD floppy and Z80DMA.) The large amount of ROM can be used as file storage (e.g. 400kB ROM-disk, so the interface is useable also without CF card nor HDD). Battery backup for RAM will be considered, if were enough space inside the case - this would give another storage, a 400kB RAM-disk. Also an idea of adding RTC appeard. Last idea is ZX128 banking support - in case the bit 4=1, the bit 4 in port 32765 (#7FFD) would swap pages in ROM/RAM mode.

For that configuration I will offer two operating systems: ZXVGS (the one for MB-02 should work without changes, however this must be tested) and CPM22QED (CP/M 2.2 compatibile). FAT16 support is expected in near ZXVGS releases (now I have some other work to finish first).

Files for download

diwi212t.jpg 453.3kB (2006-12-22 23:00)

Printed circuit board of DiwIDE v212, top view. The soldermask is over CF mounting pads.

diwi212b.jpg 430.7kB (2006-12-22 23:01)

Printed circuit board of DiwIDE v212, bottom view.

diwi-212.zip 83.3kB (2006-11-21 16:31)

(old) DiwIDE v212 in Eagle data files. Uses original GAL programming. Some things need to be corrected (are in v213).

Links to other pages

See also

PL3MEM - ZX Spectrum IDE (ATA)

External box for ZX Spectrum with 128kB EPROM, 32kB SRAM in ZX+3 switching and 16b IDE interface.

YAMOD.ATBUS 8bit IDE

The fastest 8bit universal IDE multiplexer for YABUS. Includes RTC type DS 1287, DS 12887 or MC 146818.