From: Jarek Adamski Date: 2006-03-24 19:39:42 Subject: ZX1541 - interface for ZX81 to Commodore 1541 disk drive URL: http://8bit.yarek.pl/interface/zx81.zx1541/ Technical description. The interface has two memory chips: - 62256 SRAM (32kB), - 28C64 EEPROM (8kB). The logic is made of following chips: - 74*174 latches 6 bits of data (port #BF), - 74*365 allows to read 6 bits of data (port #BF), - 74*139 decodes memory control signals, - 74*32 4×OR decodes port address and memory signals, - 74*06 6×NOT open collector drives IEC lines and LEDs. Beside some transistors and resistors are used to make simple gates, and 8×1N4148 diodes to protect IEC lines. 1. The port address is decoded on OR gate (74*32) from /IORQ and A6, exactly as in original design. The product is called /BF signal, what means #BF (#xxBF) address. Other addresses with A6=0 are possible, but not recommended. 2. /BF signal is used directly to control 74*366 buffer together with /RD signal (74*365 has internal OR gate). Second OR gate (74*32) used on /BF and /WR produces /BFWR signal to latch data into 74*174. 3. 74*174 has reset generator that works only on power-up. This enables the interface and selects memory bank 0. See below. 4. 8kB of 28C64 EEPROM is seen in #2000..#3FFF addresses. The EEPROM is write-protected, when its jumper is open. To update software close the jumper, then open it again. No extra voltage source is required to reprogram this EEPROM. 5. 32kB of 62256 SRAM is seen in #8000..#BFFF addresses, as two 16kB mutually exclusive banks. Only one of them can be used at a time - which is selected by bit 1 in port #BF. This bit generates MA14 signal that can be read back as bit 1 of #BF port. 6. Both SRAM and EEPROM access are disabled when bit 0 is set in value outed to #BF port. This allows to use other interfaces connected between ZX81 and ZX1541. The bit 0 generates signal called Q0. Q0 is inverted by NOT gate (74*06), giving /Q0 signal. 7. Memory addresses are decoded by third OR gate (74*32) and half of 74*139 decoder. A13 and A15 lines are ORed to give A13G signal that can be low only for A15=0. For A15=1 is high. In A14 line is inserted a resistor, this allows the "next" interface connected to through slot to disable ZX1541 memory. The "next" interface can pull up to +5V the DISIN (incoming /ROMCS on edge slot) line by a NPN transistor, exactly like with pure ZX81. The A13G, DISIN (A14 after resistor) and A15 lines are connected to the decoder. This produces three output signals: /000, /001, /10X - see this table (n.c. means not connected or not pulled up by "next" interface): DISIN A15 A14 A13 A13G /000 /001 /10X - addresses n.c. 0 0 0 0 0 1 1 - #0000..#1FFF n.c. 0 0 1 1 1 0 1 - #2000..#3FFF n.c. 0 1 0 0 1 1 1 - #4000..#5FFF n.c. 0 1 1 1 1 1 1 - #6000..#7FFF n.c. 1 0 0 1 1 1 0 - #8000..#9FFF n.c. 1 0 1 1 1 1 0 - #A000..#BFFF n.c. 1 1 0 1 1 1 1 - #C000..#DFFF n.c. 1 1 1 1 1 1 1 - #E000..#FFFF >+2V x x x x 1 1 1 - #xxxx..#xxxx 9. Interface disables internal ROM decoding of ZX81 by pulling up to +5V the DISOUT line (outgoing /ROMCS on edge slot) with NPN transistor. The transistor is controlled by the fourth OR gate (74*32). So two signals can disconnect internal ZX81 ROM independently. One of them is DISIN, which is used by "next" interface to disable both ZX1541 and internal ZX81 ROM. The second signal is generated by AND gate made from resistor and open collector inverter (74*06). So both /000 signal and /Q0 must be in high state to disable the internal ROM of ZX81. /000 is high for all addresses except #0000..#1FFF and /Q0 is high until 1 is written as bit 0 into #BF port. This means, the internal ZX81 ROM is not disabled only for addresses #0000..#1FFF as long as DISIS is not pulled up by "next" interface ("-" means high impedance, "0r" and "1r" means state set by resistor). DISIN Q0 /000 /Q0 OR DISOUT - addressess n.c. 0 0 0r 0 - - #0000..#1FFF n.c. 0 1 1r 1 1 - #2000..#FFFF n.c. 1 x 0 0 - - #0000..#FFFF >+2V x x x 1 1 - #0000..#FFFF 10. Signals /001 and /10X are used to activate EEPROM and SRAM. This is done with second half of 74*139 decoder and OR gate made from resistor and NPN transistor. Resistor is inserted in /MREQ line giving /MEM signal. /MEM signal can be pulled up by the Q0 line (and transisor) when the ZX1541 has to be disabled by setting bit 0 in #BF port. When not disabled, /MEM signal works like /MREQ: Q0 /MREQ /001 /10X /MEM /EEPROM /SRAM - adresses 0 0 0 1 0 0 1 - #8000..#BFFF 0 0 1 0 0 1 0 - #2000..#3FFF 0 0 1 1 1 1 1 - other than above 0 1 x x 1 1 1 - #0000..#FFFF 1 0 x x 1 1 1 - #0000..#FFFF 1 1 x x 1 1 1 - #0000..#FFFF 11. Bits 2, 3, 4, 5 of value outed to #BF ports can force low state on IEC lines /RESET, /ATN, /CLK, /DATA when are set to 1. When these bits are written as 0, IEC lines are in high state unless other IEC interface forces low state with open collector output gates. Lines are pulled up to +5V by 1kohm resistors, while 1N4148 diodes force the IEC voltage to be in range -0.7V to 5.7V. 12. IEC lines can be read in bits 4, 5, 6, 7 in #BF port, /RESET, /ATN, /CLK, /DATA respectively. In original design only /CLK and /DATA lines were available, so the ZX81 wasn't able to act as IEC slave device (as a controller, terminal device, perhaps 1541 simulator). 13. Two LEDs are added. One lights when DISIN is high, what means interface is disabled. It should blink very fast in normal using, get dark while IEC operations and ligh continously when "next" interface disables ZX1541. Second LED is connected to IEC data line and shows the IEC is sending data. Third diode could be connected to Q0 signal showing the interface is software disabled. Mounting ZX1541 on Split interface. (To be continued.)