8bit Projects For Everyone


 
Autor Wiadomość
Jarek Adamski
Site Admin


Dołączył: 2004-09-08
Posty: 190
Skąd: Poland 52N 19E

Wysłany: 2005-08-12 14:47    Temat postu: Internal memory upgrade for Timex 2068. Odpowiedz z cytatem

I try to design a simple internal memory upgrade for TS2068 and TC2068. I want to use 512kB SRAM, seen in EXROM/Dock and 128kB PEROM (29C010), seen in Home/EXROM.

This is a request for comments.

128kB PEROM in Home and EXROM

For the Home ROM bank switching I've dicided to use my 4MB switching scheme. So, the responsible port is #D0. The solution is called FlashD0 and is also available for other Spectrum models, except the EXROM feature.

Bit 7 enables the ROM when set to 1 (0 selects the RAM bank, not present in this upgrade), except just after reset (until first write to #D0 port), when the ROM is forced to be seen. Bits 0..2 of #D0 select one of eight 16kB ROM pages seen in Home. Except the normal bank selection, the PEROM page can be changed with some extra conditions regarding bits 5 and 6.

A14 line of PEROM can be controlled with bit 4 in #7FFD port, when ZX128 compatibility upgrade is installed. This happens when bit 5 in #D0 is set and gives two ZX Spectrum 128K ROM banks.

A15 line of PEROM can be controlled with /M1 line, but only when bit 6 is set. This gives a possibility to emulate TR-DOS, as it has entry points in area of character set (#3D00..#3DFF), so switching with /M1 gives other data for normal reading and other for jumps in that area.

The PEROM is also seen in EXROM. But in this case, A16 line of PEROM is controlled by Home/EXROM selection (0 for Home, 1 for EXROM) while A14 and A15 lines are connected to Z80 ones. So in the EXROM only last 4 pages are seen (4,5,6,7), as 64kB filling whole EXROM bank.

The contents of PEROM pages can be as below; after the "<->" sign is the extra switching explained
page 0: TS2068 ROM <-> /ROMCS=1 to page 4
page 1: TR-DOS traps for ZXVGS <-> /M1=1 to page 3
page 2: ZXVGS system page
page 3: ZXROM for ZXVGS <-> /M1=0 to page 1
page 4: EXROM (8kB) <-> /ROMCS=0 to page 0 (Home)
page 5: pure ZXROM (48K)
page 6: ROM0 of ZX128 <-> bit 4,(#7FFD)=1 to page 7
page 7: ROM1 of ZX128 <-> bit 4,(#7FFD)=0 to page 6

The computer starts from page 0. At this moment, the standard 2068 ROM is used. It can be modified slightly to display "boot menu", using remaining 8kB of the page 4 (the "original EXROM" one). Value written to #D0 port should be #80.

When you select ZXVGS mode, the pages used are 1, 2 and 3. Page 3 (#C1 or #C3 is written to #D0 port, bit 1 has no matter) works as ZX Spectrum 48K ROM, but opcodes are taken from page 1 (/M1=0). Page 2 (#82 written to #D0 port) is selected when ZXVGS functions are called. ZXVGS is operating system, that can control mass storage devices like FDD, HDD and file server connected with cable.

Also, ZX Spectrum 128K mode can be set. In this mode, pages 6 and 7 are used. (#A6 or #A7 is written to #D0 port, the bit 0 has no matter.)

Alternatively, pages 4, 5, 6 and 7 can be used as 64kB ROM in EXROM bank. In this case the ZX Spectrum 128K configuration must be removed or replace the ZXVGS one.

512kB SRAM in EXROM or Dock

Separate problem is the 512kB SRAM. I want it to be seen in EXROM and optionally in Dock. My assumptions are that the RAM should:
- be compatibile to ZXVGS UPB upgrade (32kB RAM in lower 32kB of EXROM) - beside ZXVGS, this configuration can be used by CPM22QED UPB (CP/M) without extra cartridges,
- offer 32kB RAM in upper 32kB of EXROM, what is intended to work in 2068 ROM mode,
- be compatibile to Larken ramdisk (8 pages of 32kB, in upper 32kB of Dock, switched with bits 0..2 of #07 port),
- coexist with Larken ramdisk cartridge located in Dock,
- have higher priority in EXROM than above PEROM.

Any suggestions are welcome.
Powrót do góry
Zobacz profil autora Wyślij prywatną wiadomość Odwiedź stronę autora Yahoo Messenger
Jarek Adamski
Site Admin


Dołączył: 2004-09-08
Posty: 190
Skąd: Poland 52N 19E

Wysłany: 2005-08-21 21:51    Temat postu: 512kB SRAM solution. Odpowiedz z cytatem

The internal construction shows that it isn't possible to use EXROM cartridges without internal changes, because the EXROM ROM chip fills whole 64kB (repeated 8 times). EXROM cartridges would cause conflict in the unmodified TS2068. The /EXROM signal is useless both on cartridge and rear slots, as no extra memory can be paged, because there's no way to disable the internal EXROM memory. /BE=0 disables all memory and also keeps the /EXROM high. However, the external EXROM addresses are available for writing-only without conflict, but this is useless.

There are 3 options for the SRAM:
- is seen in EXROM or in Dock,
- is seen in upper 32kB or not (ROM in EXROM, cartridge in Dock),
- is seen in lower 32kB or not (ROM in EXROM, cartridge in Dock).

Because this is internal upgrade, it is possible to modify the /ROSCS signal outgoing to cartridge slot, and disable it while the SRAM is paged in, so no conflicts may happen.

There are 3 signals that control the behaviour:
- /EXROM is 0 while access to EXROM bank,
- /ROSCS is 0 while access to Dock,
- A15 is 0 for lower half and 1 for upper one.

3 bits (0, 1, 2) of the latch select one of 8 SRAM pages (64kB each). Bit 6, when set, removes the SRAM write protection. Assuming the latch is 6bit, 2 bits are for configuration.

Absolute needs for the SRAM:
- seen in lower half of EXROM (ZXVGS, CPM22UPB),
- seen in upper half of Dock (Larken ramdisk),
- seen in upper half of EXROM (some compatibility?),
- seen in whole Dock (may be useful).
Powrót do góry
Zobacz profil autora Wyślij prywatną wiadomość Odwiedź stronę autora Yahoo Messenger
Jarek Adamski
Site Admin


Dołączył: 2004-09-08
Posty: 190
Skąd: Poland 52N 19E

Wysłany: 2005-08-21 22:09    Temat postu: Final idea for 512kB SRAM Odpowiedz z cytatem

This is the final conception of simple 512kB SRAM switching. The SRAM can have battery backup.

SRAM configurations are limited to 4 possibilities, in each there are 8 separate pages:
- 64kB Dock,
- top 32kB Dock - Larken ramdisk compatibile,
- 64kB EXROM - for ZXVGS UPB compatibility,
- top 32kB EXROM (extra compatibility).

When SRAM is mapped to Dock, has higher priority than cartridges. SRAM must be mapped to EXROM to access contents of Dock cartridges. SRAM mapped to EXROM has higher priority than PEROM available in EXROM.

The power-on configuration, due to Larken ramdisk compatibility can be only the top 32kB Dock. This will stop AROS cartridges, but the SRAM can be paged to EXROM, cardridge contents can be copied to SRAM, then after reset (or power-on with battery backup) we get the same effect as using the cardridge.

The SRAM is controlled by two out-only ports. The #0F one works always and the #07 is available only when SRAM is mapped to Dock. The power-on value for the port is #00, what gives page 0 and write-protection (Larken ramdisk compatibility).

Because the need for the Larken ramdisk compatibility, writing values #00..#07 and #40..#47 must select the top 32kB Dock configuration. The latch is 6bits wide, as Larken ramdisk uses 4 bits (0..2 for page selection and 6 for write-protection) and the memory configuration selection needs 2 bits more.

Extra bits are:
- bit 7 - when set, moves the SRAM to EXROM and disables #07 port - so external Larken ramdisk can be used without memory and port conflict.
- bit 5 - when set, enables the SRAM in bottom 32kB.

These 2 bits are reseted at power-on, what forces Larken ramdisk compatibility. However, with extra logic (inverters) it is possible to get another power-on configuration. The question is: is there a need?

The hardware

As mentioned before, the latch is 6bit - something like 74LS174. The port address decoder can be build of 74LS138, with help of diodes and resistors to allow A7, A6, A5, A4, A3, /IORQ and /WR to be decoded and transistor to switch the port #07 availability (when bit 7 in latch is set, the #07 port gets blocked). The final chip is 74LS151 multiplexer, where bits 5 and 7 of latch and A15 of Z80 select the /ROSCS or /EXROM that enables the SRAM. /MREQ is provided with diode or transistor.

All above elements should fit on small board placed under SRAM chip (74LS151 as DIL, other as SMD).

74LS151 configuration:
Kod:
bit
7 5 A15 Y
- - --- -
0 0  0  1       - none in bottom 32kB
0 0  1  /ROSCS  - top 32kB Dock
0 1  0  /ROSCS  - 64kB Dock
0 1  1  /ROSCS  - 64kB Dock
1 0  0  1       - none in bottom 32kB
1 0  1  /EXROM  - top 32kB EXROM
1 1  0  /EXROM  - 64kB EXROM
1 1  1  /EXROM  - 64kB EXROM


When Y output enables SRAM (low state), the /Y output locks PEROM and /ROSCS line available in cartridge and edge slots. Also /EXROM line on these slots could be locked, but this has limited sense, since extra EXROM memory connected to unmodified TS2068 would cause conflicts.

This upgrade doesn't stop the possibility of installing 4MB RAM upgrade in Home bank.
Powrót do góry
Zobacz profil autora Wyślij prywatną wiadomość Odwiedź stronę autora Yahoo Messenger
Wyświetl posty z ostatnich:   

© 2009-12-28 21:50 Jarek Adamski, http://8bit.yarek.pl