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Would you like to have Amstrad CPC64160?

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CPC4MB RAM upgrade

After upgrade the CPC has 4160kB RAM in total. Extra memory is seen as 64 banks of 64kB each. Upgrade is compatibile to external 512kB RAM interfaces by Inicron (RAM-BOX), DK'Tronics' and Dobbertin - as long as #7Fxx port is used.

Bank number is set by 3 address lines A8, A9, A10 and 3 bits: D3, D4, D5 of value OUTed to #7xxx port (#78xx, #79xx, #7Axx, #7Bxx, #7Cxx, #7Dxx, #7Exx, #7Fxx).

OUT %01111bbbxxxxxxxx,%11bbbccc

In above format, six digits "b" mean bank number 0..63, three "c" is configuration 0..7 and eight "x" must be set to a value 0..255 that avoids possible conflicts.

Software

This 4MB RAM upgrade is supported by FutureOS Version .8.

Hardware

Upgrade is made of 3 boards, one separate logic chip and OR gate made from 2 NPN transistors and resistor. Two boards replace bank 2 and contain 4MB DRAM. The third one is mounted under Z80 and handles switching of 64 banks. Boards are connected with 2×3 wires.

Control signals for new memory: /RAS1' and /CAS1' are generated from control signals for bank 2: /RAS1 and /CAS1.

The 74LS153 generates two signals. One is /CAS1', used to access the memory and for refreshment. Second is /244, used to open 74LS244 buffer while writing.

The /CAS1' is low in Z80CPU refreshment cycles (/RFSH=0). While writing to new RAM, the falling edge of /CAS1' is delayed by 80-100ns to /CAS1 generated by PAL chip, because must wait for /WE line to be set low. While reading the dealy doesn't matter.

The /244 opens 74LS244 buffer also while memory writing (/CAS1=0 and /WE=0). This is done because the new memory doesn't have separate input and output of data lines as 4164 chips.

The OR gate made from 2 NPN transistors and resistor forces high stateon /RAS1' when /RAS=1 or /MREQ=1. While reading and writing to memory the /MREQ is 0 and only /RAS matters. But /MREQ=1 forces /RAS1' to be high in refresh cycles, so together with /CAS1' generation this makes correct CBR refreshement.


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Files for download

cpc4mb2.jpg 158.8kB (2006-06-27 18:24)
CPC6128 board prepared for upgrade - three upgrade boards are removed.
cpc4mb1.jpg 225.4kB (2006-06-27 18:03)
CPC6128 board upgraded with CPC4MB - 4MB RAM for CPC. Z80CPU is removed for better view.
cpc4mb3.jpg 78.5kB (2006-06-27 18:23)
Three upgrade boards - top view.
cpc4mb4.jpg 89.5kB (2006-06-27 18:21)
Three upgrade boards - bottom view.
cpc4mb1.zip 29.9kB (2006-04-03 21:28)
First board version of 4MB RAM upgrade for Amstrad CPC. Eagle and Tango PCB data files.
cpc4mb-r.png 4.6kB (2005-04-01 04:52)
See the CPC4MB CBR memory refreshment cycles inside Amstrad CPC. Vertical lines separate Z80CPU instruction cycles.
cpc-t.png 4.4kB (2005-04-01 04:51)
See the memory access cycles inside Amstrad CPC. Vertical lines separate Z80CPU instruction cycles.

Links to other pages



See also

DRAM
Dinamic Random Access Memory (DRAM). Memory with multiplexed address lines.
Amstrad CPC
Amstrad CPC - main board types, ROMs.
SymbOS / CPC
Multitasking and graphics support operating system for CPC.
FutureOS / CPC
Operating system for Amstrad CPC.
Memory Card : Amstrad Schneider CPC
Memory cards and interfaces for Amstrad (Schneider) CPC. dk'Tronics Silicon Disk.

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© 2009-12-28 21:50 Jarek Adamski, http://8bit.yarek.pl