ZX Spectrum memory upgrade: 4MB RAM

Overview

ZX Spectrum 128K compatibility (except AY sound).
Pentagon 512kB compatibility.
Kind of Sinclair Z88 Cambridge Computer compatibility.
ROM simulation in RAM. Other ROM contents can be loaded into RAM, then paged as ROM.
Sam Coupe compatibile write protection of section A.
Architecture ready to use operating systems like CP/M, UZI (UZIX, UZIX2), +3e, NeOS, ZXVGS.
Optional access to ISA cards with own memory.

Technical details

Section - 16kB of Z80CPU address space.
Bank - number written to configuration port.
Page - substantial 16kB of memory.

The 64kB memory available for CPU is divided into 4 sections of 16kB each, called A, B C and D (A is #0000..#3FFF, D is #C000..#FFFF).

For each section one of 256 banks is selected. Banks #00..#7F (0..127) are RAM common to all sections, banks #80..#FF (128..255) may be not common.

In present version of this upgrade for ZX Spectrum banks #80..#FF (128..255) in section A are dedicated ROM pages, in section B are reserved to access ISA architecture, in sections C and D are common RAM pages. In future banks in sections C and D may be separated, giving extra 2MB RAM.

ZX Spectrum 4MB memory upgrade map
Port address	byte outed	#00..#7F 0..127	#80..#FF 128..255
#D3 211	section D #C000..#FFFF	128 RAM pages (2MB) common to all sections	128 RAM pages (2MB) common to sections C and D
#D2 210	section C #8000..#BFFF		128 RAM pages (2MB) common to sections C and D
#D1 209	section B #4000..#7FFF		128 pages - access to ISA architecture
#D0 208	section A #0000..#3FFF		16 ROM pages of FlashD0 with 3 configuration bits

Using the banks

In ZX Spectrym 128K compatibility mode are used 8 banks numbered #10..#17 (16..23). Pentagon 512kB compatibility includes also another 24 banks: #50..#57 (80..87), #90..#97 (144..151) and #D0..#D7 (208..215). However, by writinng to #7FFD (32765) port 32 more banks can be accessed: #30..#37 (48..55), #70..#77 (112..119), #B0..#B7 (176..183) and #F0..#F7 (240..247).

Banks #00..#0F (0..15) are dedicated for ROM simulation, as it is in Z88 computer. Banks #18..#1F (24..31) are not used in Z88. Bank #1F (31) is dedicated to store allocation information about for every bank.

Operating systems, dedicated to run software written for ZX Spectrum should not use for own purposes any bank accessible with the #7FFD (32765) port. For CP/M, it is recommended to use banks #40..#43 (64..67) as basic memory, and following #44..#4F (68..79) for code and buffers.

I/O ports for memory control

Banks for sections are controlled by following ports:

#xxD0 - selects bank for section A (default is #97 = ROM),

#xxD1 - selects bank for section B (default is #15),

#xxD2 - selects bank for section C (default is #12),

#xxD3 - selects bank for section D (default is #10),

#xxFA - bit 7 when set write protects RAM in section A,

#4xFD - like #5xFD

#5xFD - similar to #7xFD, but also forces bit 6 =0 for better ZX128 compatibility,

#6xFD - like #7xFD

#7xFD - selects bank for section D, but forces bit 3 =0 and bit 4 =1, what reduces number of banks available in this way to 64 (1024kB).

The banks with screens of ZX128 are #15 (21) and #17 (23). They are duplicated, so writing goes to both video memory and 4MB RAM bank, while reading is only from 4MB RAM bank.

RAM bank in sections B and C has default setting to #15 (21) and #12 (18) pages respectively, so they don't have to be initialized by writing to #D1 (209) and #D2 (210) ports. However, bank in section D must be initialized by writing to #7FFD (32765) or #5xFD port.

Writing to any of #D0..#D3 (208..211) ports disables the default setting, so for the first time after reset all 4 ports must be written to get stable configuration.

The anterior - ZX512

The 4MB RAM upgrade is the succesor of the ZX512 upgrade. The idea was to replace lower 16kB DRAM with the 32kB DRAM taken from upper bank. Then, in upper bank 41256 chips were installed giving 256kB. Next 256kB in 41256 chips could be soldered over the first chips, but with /CAS pin bend up. The video memory was write-only and duplicated.

Port #7FFD worked as in ZX Spectrum 128K and Pentago 512kB - extra banks could be accessible with bits 6 or 7 set. Writing to #5xFD port forced the bit 6 to store 0.

Only one prototipe was made. To limit amount of wires, all logic chips were mounted on a board inserted into ULA socket, while ULA was inserted into the board.

An optional circuit on the board was dedicated to generate "high color" screen, where attribbutes are takes from another 6kB area, like in Timex and Sam. This feature was never tested.

Next board versions

Two prototipes were build basing on board version v001. Unfortunately it apperd that resistors used to set bank numbers in sections A..C cause problems. Bank number (lines O0..O7 on schematics) are set too late and ULA doesn't have enough time to stop clock cycle before low state on /MREQ line appers. This was solved (v006) by adding a buffer that controls lines O0..O2 and O7 in sections A..C. Lines O3..O6 are still set with resistor, but until activation their state is fixed and in every section the same. So befere activation we have only 256kB (via #7FFD port).

Beside the buffer working until activation, other solutions are possible. Verion v106 assumed the proper bank numbers are written while the CPU reads 4 following memory addresses (#0000..#0003). The initializer would be disabled by first writting to memory. This solution seems to be perfect, however needs many extra logic chps. Perhaps it will be done in version with GAL chips... In version v206 the second multiplexer used to create the written value was replaced with 3-state buffer and resistors.

But the winner version is v315. In this version bank number is set as in v006. In addition a several simple logic gates are replaced with one 74LS151 multiplexer. Beside, on the boards were placed two chips, that in version v001 had to be mounted separately and connected with wires.

As next, a board mounted under Z80CPU will be made. This will allow to install ZX4MB inside Timex computers, ZX Spectrum 128K, ZX Spectrum +2 and many others.

Also external interface with own CPU is expected.

Related informations

Also, for the 4MB RAM upgrade is designed (not obligatory) support for 128kB PEROM - FlashD0. It's #D0 port selects ROM bank and can disable/enable both ROM bank switching via bit 4 of #7FFD port and using /M1 as bank selection (TR-DOS traps). See links below for details.

Many thanks to Wojciech Apel, whose article "ENIAC'owe Spectrum" described memory upgrades in details and was inspiration for me.

Jarek Adamski

Files for download

zx4mb-3b.jpg 198.9kB (2006-05-23 21:59): 3rd ZX Spectrum with 4MB RAM. Main board bottom view.
zx4mb-3t.jpg 164.5kB (2006-05-23 21:49): 3rd ZX Spectrum with 4MB RAM and FlashD0 128kB PEROM. Main board top view.
howto-en.txt 7.4kB (2006-06-06 13:43): [en] Description of upgrade installation.
zxi6-315.zip 73.0kB (2006-04-03 21:09): Second 4MB memory upgrade board (v315) for ZX Spectrum ISSUE 6A. Eagle and Tango PCB data files. Two errors in tracks.
zx4mb-2t.jpg 127.0kB (2006-02-17 13:40): Second ZX Spectrum with 4MB RAM. Beside this: FlashD0 128kB PEROM, ZXMUX multiplexer, video output, keyboard pin slots, not original beeper. Main board top view.
zx4mb-2b.jpg 154.5kB (2006-02-17 13:43): Second ZX Spectrum with 4MB RAM. Main board bottom view.
work-pl.txt 8.1kB (2006-05-23 04:45): [pl] Opis działania rozszerzenia (w trakcie pisania).
problem.html 1.7kB (2006-01-14 14:30): [en[ Description of A15ULA input late setting problem.
zx4mb-1.jpg 38.5kB (2005-03-03 16:51): First ZX Spectrum with 4MB RAM. Beside this: 32kB EPROM, keyboard pin slots.
zxi6-001.zip 56.9kB (2004-07-30 02:48): (old) First 4MB memory upgrade board (v001) for ZX Spectrum ISSUE 6A with a lot of bugs. Eagle data files.

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