Clock signal CLK shown here is reversed to the one provided to Z80. So every tact starts from falling CLK=\ edge. Analyse is made from the brown vertical line on the left.
  1. The first two tacts is reading opcode from the ROM: A14Z80=0, A15Z80=0, and both /RD=0 and /ROMCS=0 strobe is generated. There should be also /M1=0, but is not shown. A hazard is noticed on /RESET line. (The opcode first reads 2 bytes, then reads byte from another location.)
  2. Next two tacts is refershment cycle (/RFSH=0) - also generates /ROMCS=0, but this has no matter, as /RD=1. In the same time ULA access screen memory, reading 4 bytes (/CAS=0) in two /RAS=0 cycles.
  3. Next 3 tacts is reading byte from non-screen memory (A15ULA=1, A15MUX=1).
  4. Next 3 tacts is reading another byte from non-screen memory (A15ULA=1, A15MUX=1). Cyan vertical line is after first tact of the 3. Since 2nd tact of this cycle starts screen reading. In the last two tacts two screen bytes are read (one /RAS=0, two /CAS=0).
  5. The problem appears as next. In case of A15Z80=0 and A14Z80=1 the ULA would stop the clock signal (on unmodified ZX Spectrum). But the A15ULA=\ is delayed to A15Z80=\ too much, so the clock is stopped too late, what creates an 60ns clock strobe, marked with red arrow. There's access to screen memory, both the used by ULA and the duplication.