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Flash D0 - 128kB PEROM

This upgrade is made as support for ZX4MB upgrade (4MB RAM for ZX Spectrum), however can work without it. Target machines are Spectrum compatibile computers, but can be used in other constructions that use 16kB ROM.

  • Starts from ROM page 0.
  • Can support TR-DOS traps (TRETRAP).
  • Can support bit 4 of #7FFD port of ZX128 ROM switching.
  • Can be disabled with /ROMCS=1 on edge slot.
  • Needs /CS to include /MREQ.
  • Is dedicated for 29C010 or 29F010 memory (128kB).
  • 29C020 or 29F020 (256kB) memory can be connected with a bit modified scheme (1 bit latch more and other powering solution, maybe next version with GAL).
  • 29C040 or 29F040 (512kB) can be used with some extra logic.
  • Can work without the 4MB RAM extension - has simplified port decoder.
  • Can include ZXVGS with small romdisk (32kB to 64kB).
  • Can setup 4MB memory banks after a reset.


The FlashD0 board can work with EPROM, Flash EEPROM and PEROM chips. The difference is functionality of writing. EPROM chips (e.g. 27C010) cannot be programmed in-system at all (they require EPROM programmer hardware). In Flash EEPROM (e.g. 29F010) a sector of 16kB or 32kB can be erased then programmed. This can be done, but takes some noticeable time and large RAM buffer is required to temporary store unchanged areas. In PEROM (e.g. 29C010) sector size is 128 bytes, what allows to use such memory in similar way as a floppy disk.

Bits 0..3 - ROM page

One of 16 ROM pages can be selected (with 29C020 PEROM). In case of 29C010, pages 0..7 are the same as 8..15.

When the ZX4MB upgrade is also mounted, there's no need for more ROM pages. ROM can be simulated by write-protected RAM. But the write-protected RAM pages cannot support ZX128 ROM bankswitching nor TR-DOS traps.

Bit 4 - write-protection

For better safety there's hardware PEROM write-protection. When bit 4 in #D0 is reset, PEROM is protected. When writing is enabled, any write will probably not damage the PEROM contents, but switches PEROM into poll mode, what results in compuer reset. To reprogram the PEROM, this bit must be set in bank number.

Bit 5 - #7FFD switching

The line A14 (pin 27 in 28 pin socket) should be connected via 1kohm resistor to ouput of bit 4 latched in #7FFD port, when ZX128 compatibility circuit is present. This extra switching is active when bit 5 in 208 (#D0) is set and gives two ZX Spectrum 128K ROM banks.

Bit 6 - TR-DOS traps

The line A15 (pin 1 in 28 pin socket) should be connected via 1kohm resistor to /M1 of Z80CPU. This gives a possibility to emulate TR-DOS, as it has entry points in area of character set (#3D00..#3DFF), so switching with /M1 gives other data for normal reading and other for jumps in that area.

Bit 7 - ROM/RAM selection

Bit 7 enables PEROM when is set. This is for cooperation with 4MB RAM upgrade, where values #00..#7F select RAM page.

EXROM option

For use in Timex 2068, extra EXROM input option is designed. When this input is in low state, PEROM works as normal (as above). But pulling this input to high state switches the PEROM into EXROM mode. A16 of PEROM is foced into high state and features of bits 5 (ZX128) and 6 (TRETRAP) are disabled. In the EXROM mode, to pins 27 and 1 of the socket signals A14 and A15 of Z80 should be provided (in place of bit 4 of #7FFD port and /M1) by external multiplexer. This gives a 64kB ROM block in EXROM bank, build of pages 4..7 or 12..15.

The switching hardware

There are 8 latched outputs Q0..Q7, respectively to data bus D0..D7. The exception is Q3 that always latches 1, so later is called QH. QH is set with first port write and cleared with reset (/RES=0). The PEROM is disabled (with transistor) only when Q7=0 and QH=1.

After a reset all latches are set to 0. As Q7=0 the ROM should be disabled, but is not due to QH=0. The ROM bank 0 is selected. First value written to port #D0 should have the bit 7 set (#80..#FF). Next writes to #D0 port with bit 7 reset, disable the PEROM (and page in RAM when 4MB RAM extension is present).

Value OUTed
to #D0 port
Lines of 128kB PEROM
%0xxxxxxx/ROMCS=1 (PEROM is disabled)
%101xxCBxCBA14 from socket
bit 4 of #7FFD port
%110xxCxACA15 from socket
%111xxCxxCA15 from socket
A14 from socket
bit 4 of #7FFD port

The decoder needs to decode A0=0, A1=0, /WR=0 as they are not decoded in 4MB RAM upgrade and the selection line from 4MB RAM upgrade port decoder. When 4MB RAM upgrade is not present following confitions should be chcecked: A2=0, A3=0, A4=1, A5=0, A6=1, A7=1 and /IORQ=0.

In ZX Spectrum the ULA port access must be disabled while accessing #D0..#D3 ports (A2=0 or A5=0 should pull-up the /IOULA line).

Example (recommended) memory map

  • ROM0 has modified ZXROM code that is dedicated for interfaces that doesn't initialize #D0..#D3 ports. Just after reset it switches to ROM2.
  • ROM1 and ROM3 support the TR-DOS traps (TRETRAP). ROM1 is used (selected) when opcode is fetched (/M1=0), ROM3 for data reading cycle (/M1=1). They have the same contents, except #3C00..#3FFF area, where in ROM1 are jump codes, while oridinary reading returns character set data from ROM3. ZXVGS entry points switch to code in ROM2.
  • ROM2 is the main ZXVGS code. This code uses some RAM pages to store variables. Can also test hardware or load ZXVGS code from harddisk into RAM.
  • ROM4 and ROM5 are free for romdisk files or another ROM set. (For 2068 mode, ROM4 can be filled with 8kB EXROM code and ROM5 can contain the 2068 Home ROM.)
  • ROM6 and ROM7 allow the computer to work as ZX Spectrum 128kB (when ZX128 compatibility circuit is present).

first 64kB
second 64kB
bit 4 of #7FFD port/M1=0/M1=1A15=0A15=1
ZXROM (boot)
ZXVGS code
(EXROM 2068)
ZX128 ROM0
TR-DOS traps
(2068 Home)
ZX128 ROM1

External interface that uses hardware memory traps (+D, TI-of-TTL, etc.) and activates the 4MB RAM upgrade, should write #80 (128) into #D0 (208) port for ZX48 ROM or #A6 (166) for ZX128 ROM (so bit 4 in #7FFD port select the bank).

For better safety, the pages used should be tested if they contain correct contents. For example, the FlashD0 dedicated to Timex Sinclair 2068, can have 2068 ROM in ROM0 page, and pages ROM4..ROM7 can be used for extra EXROM code.

Experiment - Microdrive simulation

FlashD0 can be also used to simulate Interface 1 with one Microdrive tape. This requires some changes in Interface 1 code (software switching and different reading and writing sector). To use is 128kB. 16kB is ROM BASIC, 8kB takes code from Interface 1. In the simplest solution 640 bytes must be reserved for a Microdrive setcor (594 bytes rounded up to PEROM sector boundary). So in 16kB will be 25 sectors and 384 bytes for code for reading and reprogramming sector, located on every PEROM page (except ROM BASIC). Totally this will give 162 sectors, what means 81kB per data.

Present version

In present FlashD0 version (v004), A0, A1, A5, A6, /WR and /IORQ are decoded. The /IORQ input should be replaced by selection line from 4MB RAM extension decoder.

When FlashD0 is mounted together with Z80JOY, there's dimensions overlap. Z80JOY must be mounted in higher position (e.g. FlashD0 soldered directly to board, while Z80JOY in extra socket).

The version v003 upgraded to v004 compatibility is working without problems in Timex Computer 2048 (with TC2144 upgrade). The /CE signal is gated by /MREQ with NPN transistor (BC337).

Flash D0 - 512kB PEROM

For a 512kB chip, set bit 3 changes bank switching, so pages are selected with bits 0, 1, 2, 5, 6.

The AT29C010 chips are no more produced in DIL case and there can be problems to buy them. To eliminate this problem, a converter-board v201 is created, allowing the PEROM in PLCC (SMD) case to be connected. In the same time there are some place for additional latch and switching circuit for AT29C040 (512kB) support. The board doesn't work alone and requires FlashD0 v003, v004 or v005 to be mounted under it.

The AT29C040 chip has sectors of 512 bytes and such amount must be reprogramed at a time.

Bit 3 - extra PEROM pages

When bit 3 is zeroed in value written to 208 (#D0) port, the circuit works in 128kB PEROM compatibility, what means pages 0..7, switched as described before. Setting bit 3 changes the switching. One of 32 pages can be streightly selected with bits 0, 1, 2, 5, 6. Pages 0..7 respond to pages accessible in 128kB mode.

PageValue written to 208 (#D0) port
for readingfor programming
ROM00%10001000 #88 136%10011000 #98 152
ROM01%10001001 #89 137%10011001 #99 153
ROM02%10001010 #8A 138%10011010 #9A 154
ROM03%10001011 #8B 139%10011011 #9B 155
ROM04%10001100 #8C 140%10011100 #9C 156
ROM05%10001101 #8D 141%10011101 #9D 157
ROM06%10001110 #8E 142%10011110 #9E 158
ROM07%10001111 #8F 143%10011111 #9F 159
ROM08%10101000 #A8 168%10111000 #B8 184
ROM09%10101001 #A9 169%10111001 #B9 185
ROM10%10101010 #AA 170%10111010 #BA 186
ROM11%10101011 #AB 171%10111011 #BB 187
ROM12%10101100 #AC 172%10111100 #BC 188
ROM13%10101101 #AD 173%10111101 #BD 189
ROM14%10101110 #AE 174%10111110 #BE 190
ROM15%10101111 #AF 175%10111111 #BF 191
ROM16%11001000 #C8 200%11011000 #D8 216
ROM17%11001001 #C9 201%11011001 #D9 217
ROM18%11001010 #CA 202%11011010 #DA 218
ROM19%11001011 #CB 203%11011011 #DB 219
ROM20%11001100 #CC 204%11011100 #DC 220
ROM21%11001101 #CD 205%11011101 #DD 221
ROM22%11001110 #CE 206%11011110 #DE 222
ROM23%11001111 #CF 207%11011111 #DF 223
ROM24%11101000 #E8 232%11111000 #F8 248
ROM25%11101001 #E9 233%11111001 #F9 249
ROM26%11101010 #EA 234%11111010 #FA 250
ROM27%11101011 #EB 235%11111011 #FB 251
ROM28%11101100 #EC 236%11111100 #FC 252
ROM29%11101101 #ED 237%11111101 #FD 253
ROM30%11101110 #EE 238%11111110 #FE 254
ROM31%11101111 #EF 239%11111111 #FF 255

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Files for download

info-en.html 18.6kB (2007-05-10 01:15)
[en] FlashD0 - user manual.
info-pl.html 20.0kB (2006-06-05 19:53)
[pl] FlashD0 - user manual.
fld0prog2.zip 16.8kB (2006-04-23 21:31)
ROM0 with programming code. Load new contens at 32768 and use USR 1460X to program X page (0..7). Only 128B sectors. Only changed sectors are reprogrammed. Added safe jumps to banks.
fld0-004.zip 33.1kB (2006-04-03 21:14)
Project v004. Added EXROM support. Eagle and Tango PCB data files.
fd0prog.zip 1.8kB (2005-08-21 23:21)
FlashD0 simple programming code. Originally written by Pera Putnik and adapted for FlashD0 (29C010 only). Works, but should test bit 6, not 7.
fld0-003.zip 25.3kB (2004-07-27 12:45)
(old) Prototipe project v003 - Eagle and Tango PCB data files.

Links to other pages

[en] Description on the forum. FlashD0 upgrade dedicated for Timex 2068 computers. Second 64kB of PEROM is seen in EXROM.
[en] Other idea for Flash by Pera Putnik - #A9 (169) port.

See also

4MB RAM upgrade : ZX Spectrum
ZX Spectrum memory upgrade - 4MB RAM (DRAM).
Two YABUS slots for Timex FDD 3000 with memory extension (4MB RAM).
ZXVGS FD0 - FlashD0 (128kB PEROM)
ZXVGS for FlashD0 (128kB PEROM) for ZX Spectrum. Works with 128kB, TC2144 and 4MB RAM. Supports many IDE and floppy interfaces.
Memories with parallel address and data lines.



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© 2009-12-28 21:50 Jarek Adamski, http://8bit.yarek.pl